Sr <= sr end else begin if (i = 'd0 ) begin Sr <= data_in //when there is no load pulse and ce = 1 we keep shifting the data end else Sr <= din end else begin if (dir ) begin if (i = SIZE - 1 ) begin
Sr <= 'd0 end else if (ce ) begin if (load_pulse ) //whenever we detect a load pulse, we load the register with new data begin if 'load' is controlled by a user button we do not know exactly for // how many cycles the button press is going to last. Module universal_shift_register # ( parameter WIDTH = 8, parameter SIZE = 3 ) ( input clk, //clock input ce, //clock enable input rst, //reset input load, //load input dir, //dir=0 => right_shift dir=1> left_shift input data_in, //serial data input input din, //parallel data input output data_out, //serial data output output dout //parallel data output ) reg sr reg load_delayed reg load_pulse //****************************************************************************** //Generating a load_pulse which lasts only one clock cycle long //This prevents uncertainity as to what value is loaded owing to //random duration of the incoming 'load' signal.
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